There are some types of transistors or amplifiers using Group-III to Group-V compound semiconductors such as a GaAsMESFET (Gallium Arsenide Metal Semiconductor Field Effect Transistor), GaAspHEMT (Gallium Arsenide p channel High Electron Mobility Transistor), and InPHEMT (Indium Phosphide High Electron Mobility Transistor), and susceptive to high-frequency oscillations due to a negative resistance appearing in a drain end output, known as a Gunn oscillation. Such the Gunn oscillation is applicable as an oscillation source of microwaves or millimeter waves, but undesirable for performances of power amplifiers to be stable and highly efficient.
In such applications using a single FET to operate as an amplifier, there is an accompanied expectation for a stable operation to be free of oscillations over a wide frequency range. However, amplifiers using a single FET have a limitation in output power level. For enhancement of amplifier power level, there are amplifiers using parallel connections of two or more FETs.
Such parallel connections of amplifiers have individual amplifiers simply bearing part of entire output power, thus affording to increase synthesized output power without undue burdens on individual amplifiers.
In spite of advantageous possible enhancement of synthesized output power relative to a single FET, parallel-connected FET amplifiers are subject to phenomena of so-called “parallel FET oscillation” or “odd mode oscillation” making them unstable. Such undesirable oscillations are caused by a self-resonant circuit composed of parasitic capacitors in FETs and inductances of wirings for FET connections.
FETs tend to be broken by odd mode oscillation currents owing to such resonant phenomena.
For suppression of such undesirable odd mode oscillations, typical parallel FET amplifiers have a resistor connected in series to gates of parallel FETs for reduction of their gate currents. However, serial connection of a resistor to the gate works to reduce also an input signal to be amplified. Hence, there is a desideratum for parallel FET amplifiers to suppress odd mode oscillations without reduction of an input signal to be amplified.
As an example for suppression of odd mode oscillation in a typical parallel FET amplifier, FIG. 1 shows use of a bypass resistor Rd0 connected between drains. Further, as an example for suppression of odd mode oscillation in a typical parallel FET amplifier, FIG. 2 shows combination of a gate bypass resistor Rg0 connected between gates, and a drain bypass resistor Rd0 connected between drains. In FIG. 1 and FIG. 2, designated at G1, D1, and S1 are a gate, a drain, and a source of an FET 1, respectively, and G2, D2, and S2 are a gate, a drain, and a source of an FET 2, respectively. In FIG. 1 and FIG. 2, the sources S1 and S2 are grounded.
For parallelization of the FET 1 and the FET 2 in FIG. 1, the gate G1 of FET 1 and the gate G2 of FET 2 are connected to each other, there being inductors Lg accompanying gate wirings between the gate G1 and an input terminal Pi and between the input terminal Pi and the gate G2.
Likewise, for parallelization of the FET 1 and the FET 2 in FIG. 1, the drain D1 of FET 1 and the drain D2 of FET 2 are connected to each other, there being inductors Ld2 accompanying drain wirings between the drain D1 and an output terminal Po and between the output terminal Po and the drain D2. Further, in FIG. 1, there is a bypass resistor Rd0 connected between the drain D1 of FET 1 and the drain D2 of FET 2 (more specifically, between a node C and a node D), there being inductors Ld1 accompanying associated drain wirings.
For parallelization of the FET 1 and the FET 2 in FIG. 2, the gate G1 of FET 1 and the gate G2 of FET 2 are connected to each other, there being inductors Lg2 accompanying gate wirings between the gate G1 and an input terminal Pi and between the input terminal Pi and the gate G2. Further, in FIG. 2, there is a bypass resistor Rg0 connected between the gate G1 of FET 1 and the gate G2 of FET 2 (more specifically, between a node A and a node B), there being inductors Lg1 accompanying associated drain wirings.
Likewise, for parallelization of the FET 1 and the FET 2 in FIG. 2, the drain D1 of FET 1 and the drain D2 of FET 2 are connected to each other, there being inductors Ld2 accompanying drain wirings between the drain D1 and an output terminal Po and between the output terminal Po and the drain D2. Further, in FIG. 2, there is a bypass resistor Rd0 connected between the drain D1 of FET 1 and the drain D2 of FET 2 (more specifically, between a node C and a node D), there being inductors Ld1 accompanying associated drain wirings.
Generally, individual FETs have device variations in between, so there are potential variations developed between gate potentials or drain potentials of individual FETs. It therefore is difficult to cancel out potential variations between gate potentials or drain potentials of individual FETs, even with a bypass resistor connected between gates or drains of parallelized FETs. Further, in use for power amplification, parallelized FETs with such device variations are susceptive in power synthesis ratio to input frequencies accompanying potential variations.
Further, for parallelization of FETs, there is connection of a parallel circuit composed of a bypass resistor and a bypass inductor between gates and drains, subject to an increase in loss at frequencies of an input to be amplified.